The present invention generally relates to data processing systems, and more specifically to providing processor affinity dispatching.
A data processing system with multiple processors provides added complexities over single processor systems. These complexities are compounded when multiple processors are grouped into processor modules containing cache memories shared among the processors in a processor module.
One of the functions provided by modem operating systems is termed multiprogramming. This means that a processor is concurrently virtually executing more than one job or process at a time. This is typically done by time slicing, where one process gets control of the processor and executes for awhile. Than another process gets control and executes for awhile.
One technique that has become common in modern computer architectures is the usage of cache memories. Cache memories are much higher speed and much smaller memories than the computer""s main memory. They provide processor efficiency benefits since computer programs tend to have locality in their references to memory. This means that after a certain memory location is referenced, it is more likely that memory locations close to the referenced memory location are next referenced, compared to the remaining locations in memory. The earlier memory reference will bring a chunk of data or instructions stored in main memory into the higher speed cache memory, assuming that locations in the chunk will be referenced shortly.
Cache memory works well as long as one process has control of a processor. However, in a multi-programming operating system, the process in control of the processor will ultimately be suspended and another process dispatched on that processor. At that time, the newly dispatched process has a completely different locality. Most of its data and instructions will not be found in the cache memory, but rather in main memory.
In a data processing system with multiple processors, the processors can be organized into processor modules, with each processor module having a cache memory shared among the processors in a processor module. These processor module cache memories are typically much larger than the cache memories on-board in each of the processors. However, even though these cache memories are quite a bit larger, their utilization in a multi-programming system cause some of the same problems encountered in switching between different processes to execute. In particular, when a process is finally redispatched, it will often find portions of its data and/or instructions to be located in a processor module cache memory other than the one shared by the processor executing the process. The result is that these portions of data and instructions will have to be reloaded from main memory, or siphoned from the cache memory containing them. In either case, processor efficiency is degraded. It would be advantageous if this processor inefficiency could be reduced, resulting in increased system throughput.